Technical Specifications of TONGWEI’s Latest Silicon Wafers
Let’s get straight to the point. The latest silicon wafers from TONGWEI are primarily represented by their N-type TOPCon (Tunnel Oxide Passivated Contact) and advanced P-type PERC (Passivated Emitter and Rear Cell) monocrystalline wafers. These products are engineered for the next generation of high-efficiency solar cells, pushing the boundaries of conversion efficiency, power output, and long-term reliability. The core specifications revolve around achieving ultra-low oxygen content, exceptionally high minority carrier lifetime, and superior mechanical strength to enable more robust and efficient cell processing.
When we talk about the base material, the quality of the monocrystalline silicon ingot is paramount. TONGWEI’s latest wafers are sliced from ingots grown using the advanced Direct Czochralski method with continuous Czochralski (CCz) capabilities for N-type products. This allows for more stable and uniform doping of the silicon bulk, which is critical for high-performance N-type cells. The key material parameters are a testament to this refined process.
Key Material Parameters of TONGWEI’s Latest Monocrystalline Silicon Wafers:
| Parameter | N-type TOPCon Grade | Advanced P-type PERC Grade | Unit | Significance |
|---|---|---|---|---|
| Base Material | N-type Monocrystalline Silicon | P-type Monocrystalline Silicon | – | N-type offers higher tolerance to common impurities like iron, leading to better longevity and less efficiency degradation. |
| Resistivity | 0.5 – 3.0 | 0.5 – 3.0 | Ω·cm | Tightly controlled for optimal electrical properties and cell performance uniformity. |
| Oxygen Content | < 10 ppma (ASTM F121) | < 12 ppma (ASTM F121) | ppma | Ultra-low oxygen minimizes the formation of Boron-Oxygen (BO) complexes, a major cause of light-induced degradation (LID) in P-type cells. |
| Carbon Content | < 0.5 ppma | < 0.8 ppma | ppma | Low carbon prevents the formation of silicon carbide precipitates that can act as defects and reduce mechanical strength. |
| Minority Carrier Lifetime | > 3000 | > 1500 | µs | A direct measure of material purity and crystal perfection. Higher lifetime enables higher open-circuit voltage (Voc) and efficiency in the final solar cell. |
Moving from the bulk material to the physical wafer itself, the dimensions and geometry are precisely controlled to meet the demands of high-throughput, automated cell and module production lines. The industry’s shift to larger formats is fully supported by TONGWEI’s product portfolio.
Physical Dimensions and Tolerances:
| Parameter | Standard Specification (e.g., M10/G12 sizes) | Tolerance | Unit |
|---|---|---|---|
| Standard Dimensions (Length x Width) | 182mm x 182mm (M10) / 210mm x 210mm (G12) | ± 0.25 mm | mm |
| Diagonal | 257.3 mm (M10) / 297 mm (G12) | ± 0.35 mm | mm |
| Thickness (Final, after texturing) | 150 ± 20 | µm | |
| Total Thickness Variation (TTV) | < 15 | µm | Critical for reducing breakage during processing and ensuring uniform etching/texturing. |
| Warp | < 45 | µm | Minimizes handling issues and breakage in automated lines. |
| Bow | < 35 | µm |
The surface finish of a wafer is not just about aesthetics; it’s a functional layer that directly impacts light absorption and subsequent chemical processes. TONGWEI offers wafers with a diamond-wire sawn (DWS) surface that is optimized for either acidic or alkaline texturing. For N-type TOPCon wafers, the surface is engineered to be particularly suitable for the advanced wet chemical processes that create the ideal pyramid structure for light trapping and passivation. The surface roughness (Ra) is typically controlled to be between 0.3 and 0.6 micrometers after texturing, providing a large surface area for anti-reflection coating adhesion while minimizing surface recombination losses.
Let’s talk about what these specifications mean in the real world—the final solar cell. The ultimate validation of a wafer’s quality is the performance of the cell built upon it. TONGWEI’s wafers are designed to achieve record-breaking cell efficiencies. For their N-type TOPCon cells, average mass production efficiencies are now consistently exceeding 25.0%, with champion cells in the lab reaching over 26.1%. For advanced P-type PERC, efficiencies are pushing beyond 23.5%. This is made possible by the high lifetime and low degradation characteristics of the wafer. The open-circuit voltage (Voc), a key indicator of material quality, regularly exceeds 710 mV for TOPCon cells and 695 mV for high-end PERC cells. The wafer’s low oxygen content directly translates to significantly reduced light-induced degradation (LID), with TOPCon cells exhibiting less than 1% degradation in the first year and an exceptionally low annual degradation rate thereafter, often below 0.4%.
From a manufacturing and reliability standpoint, the mechanical strength of the wafer is non-negotiable. The stringent control over TTV, warp, and bow results in a mechanical yield—the percentage of wafers that survive the cell production line without breaking—that is typically above 99.5%. This is crucial for reducing production costs and waste. Furthermore, the wafers are certified to meet or exceed the mechanical stress requirements outlined in standards like IEC 61215, ensuring they can withstand the thermal cycling and mechanical loads experienced over a 25- to 30-year lifespan in a module. The wafers also exhibit excellent uniformity in terms of resistivity and thickness across the entire batch and even within a single wafer, with resistivity variation typically held to within ±5%. This uniformity is vital for ensuring every cell in a module performs consistently, preventing mismatch losses that can drag down the entire system’s output.
Beyond the standard specs, TONGWEI is investing heavily in next-generation wafer technologies. This includes the development of wafers for heterojunction (HJT) cell technology, which require even thinner geometries (down to 130 µm or less) and ultra-clean surfaces. They are also exploring gallium-doped P-type wafers as an alternative to boron-doped ones, which completely eliminates Boron-Oxygen induced degradation (BO-LID), offering another pathway to ultra-stable module performance. The R&D focus is clearly on pushing the limits of wafer thinness to reduce silicon consumption and cost, while simultaneously enhancing the intrinsic quality to support the efficiency roadmaps of all major cell architectures, from PERC and TOPCon to HJT and future tandem cells.